The present invention relates to a semiconductor integrated circuit and a method for manufacturing the same, and in particular, to a power integrated circuit having a structure which enables execution of wire bonding right above an active circuit region by utilizing POE (Pad on Element), namely, a pad is provided right above a semiconductor apparatus, and to a method for manufacturing the power integrated circuit.
In recent years, together with widespread use of information technology, needs for speeding up and low power consumption have been increasing to be developed as capabilities of electronic equipment such as computers, information storage devices, cellular phones, and portable cameras.
As factors which have significant influences on performances of such electronic equipment, there are core semiconductor electronic parts such power supplies, motor drivers, and audio amplifiers. As what has significant influences on performance of these semiconductor parts, there are power integrated circuit incorporating power devices. Therefore, for performance of semiconductor elements constituting the power integrated circuits, requests for further speeding up and lower power consumption have been becoming remarkable.
In the meantime, as general market requests, in addition to the above-mentioned speeding up and low power consumption, major improvements of power devices and circuit characteristics are desired. Also there are many requests and various proposals for low-cost and reliable structure and method which are enabled by formation of bond of wires and solder balls on right above the active circuit region.
Hereafter, first, conventional technology used before introduction of POE technology, namely, a technology by which a pad is provided right above the semiconductor device, will be explained briefly.
A member connecting a pad and an external lead frame is a bonding wire. As materials used for the bonding wire, pure or alloy gold, copper, and aluminum are exemplified. When gold is used as the material, the diameter of the bonding wire normally used is in a range from approximately 20 to 50 μm, and for wire ball bonding, a ball is normally mounted to a chip. Accordingly, when a ball is crushed into a typical nail-head profile by a bonding capillary at bonding work, the area of the pad should be large enough to enable securement of the ball. Since diameter of the ball in free state is typically in a range from approximately 1.2 to 1.6 times the wire diameter, the profile of a contact pad should be a square in a range from approximately 50×50 μm to 150×150 μm depending on process parameters. Further, when a solder ball is used for a connecting member, ball diameter is typically in a range from approximately 0.2 to 0.5 mm, while diameter of the contact pad should be such that the profile has an area from approximately 0.3 to 0.7 mm. Here, the expression “solder ball” does not necessarily mean that the solder contact is spherical, but diversified profiles including semispherical, half dome, cut conical shape or ordinary bump may be used. A specific profile depends on deposition technology, reflow technology, and material composition.
Further, contact pads are normally disposed in essentially straight array along with circumference of the chip, thereby consuming large area “silicon resources” (chips are predominantly produced on a substrate made of silicon semiconductor material). Recent semiconductor circuits require a large number of contact pads, and the number could reach frequently several hundreds even with ground connection and power connection alone. If signal connection is included, over 1000 contact pads are necessary, thereby sacrificing a large amount of precious silicon resources.
Further, it is known from over several years of experience that wire bonding process exerts a sizable stress to a layer under the metal and dielectric body. Causes for this are impact of bonding capillary (nail-headed contact is formed by crushing a golden ball), frequency and energy of supersonic vibration of bonding capillary and golden ball (oxidized aluminum film on the surface of exposed metal layer is broken), and time and temperature of the process (to initiate formation of inter-metal compound of gold/aluminum deposition). In order to avoid risks for generation of cracking or crater to a layer under the bonding pad due to stress during wire bonding process or stress given by device actuation after multiprobe test and assembly, design rules relating to layout of semiconductor integrated circuits, which prohibit circuit structure disposed in the region under the bonding pad and avoid the use of dielectric body materials which are easily damaged and are mechanically weak, are established in the past several years. For this reason, a large quantity of silicon resources is necessary to provide the bonding pad alone.
Against such a background, requests for speeding up and low power consumption of semiconductor integrated circuits as mentioned above are increasing together with substantial improvements of power device and circuit characteristics, and requests for low-cost and reliable structure and method which are enabled by formation of bond of wires and solder balls on right above the active circuit region.
—Speeding Up of Semiconductor Integrated Circuits—
First, factors which disturb speeding up of semiconductor integrated circuits are delay in a MOS transistor itself and wiring delay by wirings located at an upper layer thereon. Conventionally, delay in a MOS transistor itself was reduced by fine technology which made the gate length shorter. However, as delay in a MOS transistor itself is made smaller, problems associated with wiring delay are becoming outstanding accordingly.
In view of this, for the purpose of reducing inter-wiring delay, it is attempted to employ an insulation film (low-dielectric constant film) with low dielectric constant to the insulation film sandwiched between wirings. However, with low-dielectric constant film which realizes dielectric constant less than 3.0, mechanical strength is greatly reduced compared to a conventionally used silicon oxidized film, thus posing problems in assembly step responsible for packaging of semiconductor integrated circuits, especially in the wire bonding step, upon completion of the diffusion step responsible for circuit formation of semiconductor integrated circuits.
Specifically, since mechanical strength of an interlayer insulation film is not sufficient, if wire bonding is performed on the pad mounted on the semiconductor integrated circuit, impact load of the wire bonding is conveyed to the interlayer insulation film right below the pad via the pad, thereby greatly deforming the interlayer insulation film. As a result, a crack is caused to the interlayer insulation film which results in poor reliability due to separation of the pad or separation of interlayer insulation film. Further in recent years, for the purpose of reducing costs by reducing dimensions of the semiconductor elements, a semiconductor element with a pad mounted on transistors constituting an active circuit region is developed. In this case, if a low-dielectric constant film with low mechanical strength is used between wirings or for the interlayer insulation film, the transistor is damaged due to that the low-dielectric constant film is deformed by impact of wire bonding and the impact can be easily conveyed to the transistor, thereby causing poor quality.
In the meantime, according to Patent Document 1 (Japanese Patent No. 2974022), a metal layer is formed right below the pad across an interlayer insulation film, the metal layer and the pad are connected by a via, an impact exerted to the interlayer insulation film by wire bonding is then received by the metal layer and at the same time, possible deformation of the metal layer in the impact exertion direction is supported by the via. Thus, according to Patent Document 1, damage to the transistor by wire bonding is suppressed by providing a pad structure which reduces mechanical strength of the interlayer insulation film formed right below the pad.
Incidentally, when copper is adopted as the metal material, copper wiring will be formed by damascene process. If area of copper pattern having soft nature is made greatly large, its center portion is scraped by CMP (Chemical Mechanical Polishing) performed for flattening of plated copper after electroplating of the copper, and its film thickness is made very thin; this is referred to as dishing. Further, to form a fine via pattern in the lower layer, if area of copper pattern is made greatly large by thinning of film thickness of the metal layer, the copper is scraped thoroughly by CMP at some portions.
In this regard, in Patent Document 1, at formation of a second metal layer, namely at copper formation, the above-mentioned phenomenon occurs. When the center portion of the copper pattern is made thinner or copper is scraped thoroughly as mentioned above, impact of wire bonding received by the interlayer insulation film is increased and possibility of crack generation increases.
Contrarily, according to Patent Document 2 (Japanese Patent No. 3725527), a pad structure which is capable of preventing damage due to wire bonding with regard to an insulation film right below the pad and transistor is provided. Namely, a semiconductor apparatus of the Patent Document 2 comprises a first electrode comprising a conductive layer, an external connection electrode comprising a conductive layer formed on the first electrode, and a second electrode of at least one layer connected via the first electrode and a through-hole to a lower part of the first electrode, and has many convex configurations at periphery of the second electrode.
In this way, with such a structure that a metal layer (hereafter referred to as the lower layer metal) sandwiched by an uppermost layer metal and the interlayer insulation film is connected by the via, it is possible to prevent deformation or crack of the low-dielectric constant film adopted between wirings right below the pad and to the insulation film between layers due to impact of wire bonding. In other words, since the uppermost layer metal is supported by the lower layer metal against impact of wire bonding, no deformation occurs even exposed to impact of wire bonding. As a result, impact of wire bonding conveyed to the low-dielectric constant film that serves as the interlayer insulation film right below the pad is suppressed, thereby preventing deformation or crack occurrence of the low-dielectric constant film.
Further, for the purpose of preventing dishing of CMP due to area enlargement of the lower layer metal, many convex configurations are provided at the periphery of the lower layer metal, surface area of the lower layer metal is then enlarged, adhesion with the interlayer film is enhanced, and hence damage to the transistors due to impact of wire bonding can be reduced and at the same time, crack occurrence to the interlayer insulation film can be prevented.
Thus, according to the pad structure employed in Patent Document 2, damage to the insulation film right below the pad and transistors due to wire bonding is prevented and this eventually contributes to speeding up of semiconductor integrated circuits.
—Lower Power Consumption of Semiconductor Integrated Circuits—
Next, what impairs lower power consumption attempt of semiconductor integrated circuits is realization of a power integrated circuit incorporating a power device while chip area is made as small as possible by utilizing miniaturization MOS process and thus effectively utilizing chip area of semiconductor products. For such power integrated circuit, for the purpose of realizing lower power consumption, Pulse Width Modulation (PWM) driving technology is normally used for driving of the power device. With the PWM driving, reduction in ON resistance of the power device is an important process technology which results in lower power consumption.
Patent Document 3 (US 20020011674A1) proposes conventional, related art by which ON resistance of the power device is reduced as much as possible by utilizing POE technology. Namely, in a power integrated circuit which enables wire bonding right above an active circuit region portion, a plurality of contact pads are disposed right above a bus leading to electrodes of the power transistor by utilizing POE technology, and a plurality of contact pads and lead frames are connected by bonding wire. This minimizes the resistance value and current pathway from the connecting member to the electrode, thereby improving electric characteristics of the power transistor.
FIG. 15 shows a simplified plan view of a part of the semiconductor integrated circuit described in Patent Document 3 and an electrical diagram.
As shown in the plan view of FIG. 15, an active region 2 of the power transistor is formed in an IC chip 1, and on the active region 2 are formed a first bus 3 which is composed of sheet-like metal and is connected with all source electrodes, and a second bus 4 which is connected with all drain electrodes. On the first bus 3 and the second bus 4, three contact pads 5 are respectively provided and connected commonly to each of the bus. The three contact pads 5 on the first bus 3 are disposed so as to be symmetric with the three contact pads 5 on the second bus 4. A bonding wire 6 connecting each of the contact pads 5 and an external lead frame 7 is provided.
The electrical diagram shown in FIG. 15 schematically shows electrical features relating to operation of the power transistor brought about by disposition of a connecting member to the lead frame 7 on the power transistor. Resistance Rs across source and drain of transistor itself, spreading resistance (bus resistance) Rn10, Rn20, Rn30 on the bus and various wire resistances Rb10, Rb20, Rb30 are shown on the electrical diagram.
As shown in FIG. 15, the electric circuit viewed from the lead frame 7 is such a resistance circuit that bus resistances Rn10, Rn20, Rn30 are respectively connected in series to wire resistances Rb10, Rb20, Rb30 of three bonding wires 6 which are connected in parallel to the lead frame 7, and inter-source/drain resistance Rs of the transistor itself is further connected. In this way, by the fact that the bus resistances Rn (10 to 30) are respectively connected in series to the various wire resistances Rb (10 to 30), the bus resistances Rn (10 to 30) and the wire resistances Rb (10 to 30) are eventually connected with each other in parallel, and the whole resistance constituted of the inter-source/drain resistance Rs, the bus resistances Rn (10 to 30) and the wire resistances Rb (10 to 30) is reduced. In other words, since voltage drop relating to the inter-source/drain resistance Rs, the bus resistances Rn (10 to 30) and the wire resistances Rb (10 to 30), and corresponding device effects are lowered, transistor characteristics are improved.
However, as shown in Patent Document 3, for the purpose of minimizing the resistance value and current pathway from the connecting member to the electrode in the power integrated circuit capable of performing wire bonding right above the active circuit region portion, on each one of the buses connected with the source electrode and buses connected with the drain electrode of the power transistor are disposed a plurality of contact pads in distributed fashion so as to be located right above the power transistor.
Therefore, there was such a problem that when a large current is introduced to the power transistor, since buses connected with the electrode of the power transistor are commonly connected with each of a plurality of contact pads, current is concentrated to the power transistor, thereby giving damage thereto depending on types of the power device (e.g., power NPN transistor) and on layout of the bus connected with the electrode, and reliability of the semiconductor integrated circuit is eventually hampered.